1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a ferroelectric memory device and a driving method thereof.
2. Description of the Related Art
The use of ferroelectric thin film as dielectric film of a capacitor has been developed to overcome limitations due to the need to refresh Dynamic Random Access Memories (DRAM). A ferroelectric random access memory (FRAM or FeRAM) uses such ferroelectric thin film. A FRAM can be used as main memory in various electronic equipment having file storage and search functions, such as portable computers, cellular phones and game machines, or as a recording medium for voice or images.
In a FRAM, a memory cell comprises a ferroelectric capacitor and an access transistor. By electric polarization of the ferroelectric capacitor, a logic state ‘1’ or ‘0’ is stored in the memory cell. When voltage is applied to both ends (terminals) of the ferroelectric capacitor, ferroelectric material is polarized by the direction of a produced electric field. A switching threshold voltage that a polarization state of the ferroelectric material is changed, is a coercive voltage. To read data stored in the memory cell, a voltage is applied to generate a potential difference between both electrodes of the ferroelectric capacitor, and a logic state of the data stored in the memory cell is sensed by a change of the charge sent to a bit line.
FIG. 1 illustrates a hysteresis curve for ferroelectric material of a conventional ferroelectric capacitor.
Referring to FIG. 1, when a ground voltage Vss of about 0 volts is applied and no electric field is applied to the ferroelectric material, polarization is not generated. When voltage of both ends of a ferroelectric capacitor increases in a positive direction, a polarization level or charge amount increases to a first state point A of a positive polarization region from zero. At the first state point A, polarization is generated in one direction, and a polarization level of the first state point A has the largest value. At this time, the polarization level, namely, the charge amount that ferroelectric material retains, is represented as +Qs. Even if voltage of both ends of the capacitor falls to ground voltage Vss, the polarization level does not fall to zero but remains at a second state point B. The charge amount that ferroelectric material retains by such remaining polarization, a residual polarization level, is represented as +Qr. Then, when voltage of both ends of the capacitor reverses in a negative direction, a polarization level is changed to a third state point C of a negative charge polarization region from the second state point B. At the third state point C, the ferroelectric material is polarized to a direction opposite to the polarization direction of the first state point A. At this time, the polarization level is represented as −Qs. Even if voltage of both ends of the capacitor falls to a ground voltage Vss, a polarization level does not fall to zero but remains at a fourth state point D. At this time, the residual polarization level is represented as −Qr. When voltage applied to both ends of the capacitor increases in a positive direction, a polarization level of ferroelectric material is changed to the first state point A from the fourth state point D.
FIG. 2 is a circuit diagram of a memory cell of a memory cell array in a conventional ferroelectric random access memory.
With reference to FIG. 2, a memory cell is constructed of one access transistor M1 and one ferroelectric capacitor CFE. The access transistor M1 has a drain terminal connected to a bit line B/L, a gate connected to a word line W/L, and a source terminal connected to a first terminal of the ferroelectric capacitor CFE. A second terminal of the ferroelectric capacitor CFE is connected to a plate line P/L.
When a voltage to generate an electric field is applied to a ferroelectric capacitor having ferroelectric material inserted between two electrodes and even though the electrodes are in a floating state, a polarization direction is maintained. The surface charge of ferroelectric materials is not lost naturally through leakage. If the voltage is not applied in an opposite direction sufficiently enough for the polarization level to become zero, the polarization direction is maintained.
When a voltage is applied in a positive direction to the ferroelectric capacitor and then removed, a residual polarization of the ferroelectric material of the ferroelectric capacitor enters a state of +Qr. When a voltage is applied in a negative direction to the ferroelectric capacitor and then removed, the residual polarization of the ferroelectric material enters a state of −Qr. Herewith, a logic state indicates data ‘0’ when the residual polarization has a state of +Qr, namely, at the second state point B, and a logic state indicates data ‘1’ when the residual polarization has a state of −Qr, namely, at the fourth state point D. Thus, the difference in charge when changing from the first state point A to the second state point B (namely, a voltage corresponding to the amount of non-switching capacitance Qnsw), is distinguished from the difference in charge when changing from the fourth state point D to the first state point A (namely, a voltage corresponding to the amount of switching capacitance Qsw), thereby allowing reading of the data stored in the memory cell.
A FRAM generally operates by an external chip control signal as an external enable signal or an external chip selector signal input from the outside when a power source is supplied. When the external chip control signal is enabled, an applied external address transition is detected to control a cycle operation by using a composite pulse signal obtained by combining respective address transition detection signals (ATD). An internal clock is generated by the composite pulse signal, and read and write operations for a memory located at the corresponding address is performed. That is, when an external address is changed, a composite pulse signal is generated, and a preceding cycle operation is completed by this signal and the next cycle preparation operation proceeds. Further, an internal chip enable signal (ICE) is generated by the composite pulse signal, and all internal control signals for the operation of a memory device are generated by the ICE signal.
In such a FRAM a loss of power suffered by the external power source may cause fatal defects. In particular, during reading of the data stored at memory cells of a FRAM, data is sensed and then operation to restore the original data is performed, but in case a restoring section is insufficient and power is cut off, the existing data cannot be preserved and data is lost.
FIG. 3 is a timing diagram illustrating a normal read operation in a conventional ferroelectric random access memory.
As shown in FIG. 3, a read operation in a conventional ferroelectric random access memory (FRAM) starts by a transition of an external chip control signal XCEB from a ‘high’ logic level to a ‘low’ logic level.
An external address signal XA is applied by the enabling of the external chip control signal XCEB. The external address signal XA is applied to an address buffer circuit (not shown). The address buffer circuit buffers the applied external address signal XA and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective address signals. The address transition detection signals are added by a composite pulse signal generation circuit, and become a composite pulse signal ATD_SUM as a single address transition detection signal.
An internal chip enable (ICE) signal ICE is generated by the composite pulse signal ATD_SUM, and all internal control signals necessary for operation of a memory device are generated by the ICE signal ICE. The ICE signal ICE is not generated in a transition for an enabling of the composite pulse signal ATD_SUM, but is generated in a transition for a disabling of the composite pulse signal ATD_SUM, after all the address transition detection signals are applied.
When the ICE signal ICE is generated, a word line W/L is enabled by a word line decoder and driver circuit (not shown). Further, a plate line P/L is enabled by an enabling of plate control signal PPLS generated in response to the ICE signal ICE.
When the plate line P/L is enabled, a charge sharing section t1 starts. A voltage corresponding to data stored in a memory cell at a bit line B/L is held at a low voltage level.
Next, a sense amplifier is enabled, and the charge sharing section t1 is completed, and a sensing section t2 starts. At the sensing section t2, data at the bit line B/L is sensed and amplified by the sense amplifier.
The operation at the sensing section t2 is finished by a disabling of the plate line P/L through the plate control signal, and a write-back section t3 starts.
Herewith, the charge sharing section t1 and the sensing section t2 each have a value decided by an internal circuit.
The write-back section t3 is to restore original data so data stored in a memory cell is reversed when a plate line is enabled for a general read operation.
The write-back section t3 is maintained until the sense amplifier is disabled. The disabling of sense amplifier can be generated in response to a disabling of the plate line, and also can be generated in response to a transition for an enabling of second composite pulse signal ATD_SUM.
When the sense amplifier is disabled, the internal chip enable signal is disabled and thus the word line W/L is disabled, and the read operation is completed. Then, in a transition for a disabling of the second composite pulse signal ATD_SUM, an internal chip enable signal is again generated, and the next operation is performed.
FIG. 4 is a timing diagram illustrating a power loss during a read operation in a conventional ferroelectric random access memory.
As shown in FIG. 4, in case of an abnormal read operation, the operation to the sensing section t2 is the same as the description referred to in FIG. 3. The sensing section t2 is finished and the write-back section t3 starts to perform a restoring operation. However, when power is turned off for a shorter time than the time to perform a normal restoring operation, the ICE signal ICE is disabled. Then the word line W/L is disabled, and the plate control signal PPLS and the sense amplifier enable signal SAEN are disabled. Thus, the read operation is prematurely completed before the completion of the write-back section t3, and data stored in the memory cells is lost.
U.S. Pat. No. 5,943,257 discloses first and second detection signals having different voltage levels to indicate whether a power source of a power supply is on or off. When the power source is off, it is determined whether an external chip control signal XCE has an enabled state or disabled state. If the disabled state exists, a chip enters an off state to halt operation, and if the enabled state exists, a minimum time is maintained to complete a read operation before it enters an off state.
In such proposed technique, when the external chip enable signal XCE has an enabled state, and control signals for operations are not generated, the restoring operation in read operation is performed at a voltage lower than normal, thus decreasing sensing margin and degrading retention characteristic.